Senior FPGA/ASIC Digital Design Engineer (dvtc) English fluency (C-Level); German B-Level (C-Level preferred)
Senior FPGA/ASIC Digital Design Engineer Location: Dresden, Germany (Hybrid Work)
Employment Type: Permanent (Unbefristet)
Salary Range: €75,000 - €90,000 annually (No Bonus)
Open Positions: 2
Work Arrangement: 1 home office day per week (2nd possible for candidates outside Dresden)
Travel Requirements: Minimal (occasional customer visits within Germany)
Company Overview
The company is an R&D-driven company specialising in IoT, embedded systems, and deep tech solutions. Founded in 2017 and headquartered in Dresden, Germany, it employs around 60 people and is focused on hardware and software integration for Smart Home, Quantum Computing, and IoT devices.
Why Join ?
High Autonomy: Work on projects from scratch with ownership of key developments.
Diverse Tech Exposure: IoT, IIoT, Deep Tech, and MedTech applications.
Career Growth Paths: Opportunities for specialists, project leads, and management roles.
Strong Work Culture: Innovation-driven, flexible, and collaborative environment.
Role Overview
As a Senior FPGA/ASIC Digital Design Engineer, you will design and verify FPGA and ASIC-based SoC architectures, working on digital design, RTL integration, and debugging. You will collaborate closely with cross-functional teams, contributing to cutting-edge developments in IoT and deep tech applications.
Key Responsibilities
1) FPGA/ASIC Digital Design & Architecture
Develop and verify digital designs for FPGA and ASIC-based SoC architectures.
Perform RTL design and implementation using SystemVerilog, Verilog, and VHDL.
Work on functional unit design, RTL integration, debugging, and validation.
Utilise Xilinx Vivado for FPGA development.
2) Testing & Verification
Develop testbenches and automated test cases for design validation.
Implement verification methodologies and infrastructures for automated testing.
3) Project Management & Collaboration
Work closely with PCB design, embedded software, and sales teams to develop customer solutions.
Take ownership of project deliverables, ensuring timely milestone achievement.
Required Qualifications & Skills
Must-Haves:
7+ years of experience in FPGA/ASIC digital design (5 years in exceptional cases).
Strong expertise in RTL design, verification, and debugging.
Proficiency in SystemVerilog, Verilog, and VHDL.
Experience with Xilinx Vivado.
Ability to develop verification infrastructure.
English fluency (C-Level); German B-Level (C-Level preferred).
Nice-to-Haves:
Experience with synthesis for different target technologies.
Exposure to IoT and deep tech applications.
Leadership potential for future team lead roles.
Ideal Candidate Profile
Proactive & Responsible: Takes ownership of projects.
Strong Communication Skills: Works well in a team and cross-functional environment.
Hands-On Approach: Focused on development rather than management.
Team & Reporting Structure
Team Size: 5 engineers in the FPGA/ASIC team.
Reports To: Head of Digital Design.
Daily Collaboration With: Project managers, team leads, PCB Design, Embedded Software, and Sales teams.
Performance Indicators (KPIs)
Timely completion of project milestones in IoT and deep tech sectors.
Efficient debugging and minimal design errors.
Successful implementation of innovative FPGA/ASIC solutions.
Employee Benefits
Contract Type: Permanent (Unbefristetes Arbeitsverhältnis).
Vacation: 30 days.
Pension Contributions: €100/month (increasing to €200 with tenure).
Job Ticket or Bike Leasing: €55/month subsidy.
On-Site Fitness Studio Access.
Recruitment Process
Application
Initial HR Interview (30 min, remote): Culture & motivation check.
Technical Interview (remote or onsite): Deep dive into FPGA/ASIC expertise.
Key Selling Points for Candidates
Cutting-Edge Projects: Work on FPGA/ASIC designs in IoT, Deep Tech, and Quantum Computing.
Autonomy & Flexibility: Take charge of project development with independence.
Career Growth: Well-defined paths for technical, project, and management roles.
Stability & Benefits: Secure a permanent contract with competitive benefits.
Criteria to note:
Candidates seeking management roles instead of hands-on development wouldn't be suited. Lack of FPGA/ASIC SoC architecture experience isn't sufficient. Sole focuses on compensation and benefits rather than having a passion for working in deep tech wouldn't be an ideal fit. Silo thinking or unwillingness to collaborate wouldn't be aligned.
Apply now to be part of our innovation-driven team!
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