High-Speed Wireline Communication Researcher

Position: High-Speed Wireline Communication Researcher Location: Grenoble or Paris, France

About Us: Our research team is committed to advancing high-speed communication technologies for the future of data centers and AI infrastructure. We focus on developing cutting-edge architecture, algorithms, and system designs to push the limits of high-speed communication, enabling ultra-high-speed networks. Join us as we explore transformative solutions in wireline systems architecture, collaborating with academic and industry partners to shape the future of high-speed communications.

Position Overview:

We are seeking a High-Speed Wireline Communication Researcher with deep expertise in wireline systems architecture and algorithm design, specifically focused on Serializer/Deserializer (SerDes) PHY architecture. In this role, you will drive innovative designs for next-generation products reaching speeds up to 448 Gbps, with applications in Ethernet for hyperscale data centers and AI infrastructure.

This position is ideal for candidates interested in both of the following focus areas:

1. High-Speed Direction: Developing high-speed signal modulation and large bandwidth designs (224 Gbps and beyond), with a focus on high-speed protocol standards and physical layer design.

2. Board-Level Process Reliability: Ensuring assembly reliability for large-sized chips on PCBs, addressing challenges such as package/PCB warpage, deformation, and micro-assembly.

Key Responsibilities:

• Lead High-Speed Wireline Research: Spearhead research on high-speed wireline communication, exploring new architectures, designs, and models to enhance performance in ultra-high-speed networks.

• Algorithm Development for SerDes PHY: Design and optimize algorithms for SerDes PHY architecture, with a focus on high-speed signaling, equalization, and forward error correction (FEC) for enhanced system reliability and signal integrity.

• Modeling and Simulation: Conduct extensive modeling and simulation across large parameter spaces to refine system-level designs, ensuring optimized performance and robust board-level reliability.

• Industry Collaboration: Partner with academic and industry researchers to organize technical reviews, manage project plans, and represent the organization at international conferences and standards bodies (e.g., IEEE, OIF).

• Technology Roadmaps and Standards Engagement: Develop technology roadmaps for high-speed interconnections, aligning with IEEE 802.3 and OIF-CEI standards, and contributing to industry standards for electrical and optical communications.

• Mentorship and Knowledge Sharing: Supervise and mentor interns, PhD students, and junior engineers to support research activities and foster a collaborative knowledge-sharing environment.

Job Requirements:

• Educational Background: Master’s degree in Electrical Engineering, Information Technology, Communication Engineering, Signal Processing, or a related field; PhD preferred.

• Technical Expertise in High-Speed Communications: Proven experience with high-speed digital circuits and SerDes components, including a strong understanding of signal integrity analysis, equalization techniques, and FEC algorithms.

• System-Level Simulation Proficiency: Hands-on experience with system-level modeling and simulation for high-speed links, including proficiency with Python, MATLAB, and high-frequency simulation tools (e.g., ADS).

• SerDes PHY and DSP Knowledge: In-depth understanding of high-speed SerDes architectures (Rx/Tx), advanced equalization techniques, and DSP-level implementation for high-frequency systems.

• Standards and Protocol Knowledge: Familiarity with IEEE 802.3 and OIF-CEI standards, as well as high-speed protocols like CEI-224G, InfiniBand, DDR, and PCIe.

Preferred Skills:

• Equalization Techniques: Experience with equalization circuits such as CTLE, DFE, and de-emphasis, especially for high-speed applications (e.g., 112 Gbps NRZ and PAM).

• Academic and Industry Engagement: Strong publication record and participation in conferences, demonstrating a commitment to advancing high-speed communication technology.

• Optimization and Modeling: Background in stochastic optimization techniques and proficiency in modeling tools (Python, MATLAB, Verilog-A).

Why Join Us?

• Pioneering Projects: Contribute to transformative projects in high-speed communication for data centers and AI infrastructure.

• Collaborative Environment: Engage with a dynamic, forward-thinking team, work with leading researchers, and gain industry-wide recognition through standards development.

• Career Growth: Access professional development opportunities within a specialized technical field, and benefit from our commitment to innovation and collaboration.

How to Apply: Please submit your resume and a cover letter detailing your experience and research background. We look forward to learning how your expertise can help drive our mission to advance high-speed wireline communications.